High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible the 5th generation (5G) new radio (NR). Basing on algorithm, we propose high area-efficient encoder architecture. The proposed has advantages of and pipelined operations. Furthermore, it designed as configurable structure, fully different base graphs 5G LDPC. Thus, architecture flexible adaptability for various LDPC codes. was synthesized in 65 nm CMOS technology. According to architecture, implemented nine encoders distributed lifting sizes two graphs. eperimental results show that performance significant area-efficiency, better than related prior art. work includes whole set encoders, are Therefore, more application scenarios.